1. Field of the Invention
The invention relates to a method of, and a circuit arrangement for powering a semiconductor store, wherein the actual flip-flop transistors of the storage cells are comprised of bipolar transistors and the supply voltage, or current of which, is applied in the form of pulses in several phases.
2. Description of the Prior Art
Reference is made to U.S. Pat. No. 3,540,007 entitled "Field Effect Transistor Memory Cell" granted Nov. 10, 1970 to D. A. Hodges on Application Ser. No. 676,491, filed Oct. 19, 1967, and assigned to the Bell Telephone Laboratories, Inc.
The abstract of U.S. Pat. No. 3,540,007 reads as follows:
"A cross-coupled flip-flop stage, or memory cell, for a word oriented array of memory cells is developed from four insulated-gate field-effect transistors which perform storage, loading, and gating functions of the cell. The functions of the cell are controlled by three different voltage levels coupled by a word line to all cells of a memory word.
Associated with the array are bipolar transistor word-line-select and digit-write circuits used for achieving a low select-read-write cycle time for the memory cells".
Method of and circuit arrangements for powering storage cells whose load elements and flip-flop transistors comprise bipolar transistors are known. Also known are read/write coupling elements in the form of Schottky diodes. Thus, for example, U.S. patent application Ser. No. 662,309 (fully identified supra) describes a method of operating an integrated semiconductor store, generally of the type disclosed and described herein, in which the read/write cycles are performed in several phases, characterized in that for selecting a storage cell, a word line is pulsed to a lower level, causing the level of the bit line connected to the conductive transistor of the storage cell to be also pulled down to a lower level, whereas the level of the other bit line is raised slightly, so that the difference between the two bit line levels is sensed in a differential amplifier, that subsequently the storage cell is deselected by raising the potential on the word line as well as by applying a recovery current, so that the inner storage cell nodes are charged to a potential which in the form of a stand-by potential minus voltage drop is applied across a Schottky diode, and that the storage cell nodes are charged until one of the bit lines has reached a potential corresponding to the magnitude of the potential applied, and that finally the bit lines are returned to a common stand-by potential by switching on a voltage. The circuit arrangement in accordance with the disclosure of U.S patent application Ser. No. 662,309, for controlling the recovery and the restore phase in a read or a write cycle, is connected to the bit lines of the storage cells.
Although the storage density of highly integrated bipolar semiconductor stores can be increased substantially, this entails the problem of having to reduce the stand-by current still further at higher bit densities on the semiconductor chip. The actual read or write operations present no greater problems, although the cycle time of the store is substantially limited by the low cell current. In the case of the circuit arrangement and the method described and disclosed in U.S. patent application Ser. No. 622,309, the cell nodes are recharged relatively too slow as a result of the low currents.